Page 205 - Special Topic Session (STS) - Volume 3

STS540 Zhi Lin C. et al.
In this subsection, we compare the performance of the IC SDTS (SDTS0)
between the GR and SSGR schemes, i.e. case = 0 in Tables 2 to 4. In these
tables, we observe that the SDTS0 value increases as the ARL0 value increases.
Although the IC ATS (ATS0) values of the GR and SSGR schemes are not shown
in these tables, they can be easily computed using the formula ATS0 = n x ARL0.
For example, consider the case of n = 3, opt = 0.5 and ARL0 = 370 in Table 2,
the ATS0 = n x ARL0 = 1110. Still considering the same case, however, the
SDTS0s of the GR and SSGR schemes are 1540.00 and 1570.26, respectively,
which is around 40% greater than the ATS0 value. This result is in contrast with
the optimal EWMA and CUSUM schemes considered in Lee et al. (2013), where
they showed that the ARL0 and IC standard deviation of the run length (SDRL0)
are approximately equal. This implies that the GR and SSGR schemes have a
larger variability in the IC performance compared to the EWMA and CUSUM
schemes. This may lead to an inconsistent IC performance for the GR and SSGR
schemes. The SDTS0 comparison between the GR and SSGR schemes shows
that the SSGR scheme has a slightly larger SDTS0 compared to the GR scheme.
This indicates that the GR scheme has a slight advantage in the IC performance
compared to the SSGR scheme due to a lower variability in the time to signal
distribution.
Table 1. Optimal parameters for the GR and SSGR schemes, when n = {3, 5,
7}, opt = {0.5, 1.0, 1.5} and ARL0 = {370, 500}

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